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RT8055 ? ds8055-05 november 2012 www.richtek.com 1 ? copyright 2012 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. features z z z z z high efficiency : up to 95% z z z z z low r ds(on) internal switches : 100m z z z z z programmable frequency : 300khz to 2mhz z z z z z no schottky diode required z z z z z 0.8v reference voltage allows for low output voltage z z z z z forced continuous mode operation z z z z z 100% duty cycle operation z z z z z input over voltage protection z z z z z rohs compliant and halogen free applications z portable instruments z battery-powered equipment z notebook computers z distributed power systems z ip phones z digital cameras z 3g/3.5g data card general description the RT8055 is a high efficiency synchronous, step-down dc/dc converter. its input voltage range is from 2.6v to 5.5v and provides an adjustable regulated output voltage from 0.8v to 5v while delivering up to 3a of output current. the internal synchronous low on-resistance power switches increase efficiency and eliminate the need for an exter nal schottky diode. the switching frequency is set by an external resistor. the 100% duty cycle provides low dropout operation extending battery life in portable systems. current mode operation with external compensation allows the transient response to be optimized over a wide range of loads and output capacitors. the RT8055 is operated in forced continuous pwm mode which minimizes ripple voltage and reduces the noise and rf interference. the RT8055 is available in the wdfn-10l 3x3 and sop-8 (exposed pad) packages. ordering information pin configurations (top view) wdfn-10l 3x3 3a, 2mhz, synchronous step-down converter note : richtek products are : ` rohs compliant and compatible with the current require- ments of ipc/jedec j-std-020. ` suitable for use in snpb or pb-free soldering processes. shdn/rt gnd pgnd lx comp fb vdd pvdd pvdd lx 9 8 7 1 2 3 4 5 10 6 gnd 11 shdn/rt gnd lx pgnd comp fb pvdd vdd gnd 2 3 4 5 6 7 8 9 sop-8 (exposed pad) RT8055 package type qw : wdfn-10l 3x3 (w-type) sp : sop-8 (exposed pad-option 2) lead plating system g : green (halogen free and pb free) z : eco (ecological element with halogen free and pb free)
RT8055 2 ds8055-05 november 2012 www.richtek.com ? copyright 2012 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. typical application circuit table 1. recommended component selection v out r1 (k ) r2 (k ) r comp (k ) c comp (nf) l1 ( h) c out ( f) 3.3 75 24 30 0.47 2.2 22 x 2 2.5 51 24 27 0.47 2.2 22 x 2 1.8 30 24 22 0.47 2.2 22 x 2 1.5 21 24 18 0.47 2.2 22 x 2 1.2 12 24 15 0.47 1.0 22 x 2 1.0 6 24 13 0.47 1.0 22 x 2 22f 22f x 2 pvdd lx shdn/rt RT8055 vdd comp 2h 5v v in v out c in l1 c out gnd fb pgnd r1 r2 75k 24k 3.3v/3a r comp 30k c comp 470pf r osc 180k 0.1f c1 marking information jn= : product code ymdnn : date code RT8055gqw RT8055gsp RT8055gsp : product number ymdnn : date code jn : product code ymdnn : date code RT8055zqw jn ym dnn jn=ym dnn RT8055 gspymdnn
RT8055 3 ds8055-05 november 2012 www.richtek.com ? copyright 2012 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. functional pin description pin no. wdfn-10l 3x3 sop-8 pin name pin function 1 1 shdn/rt shutdown control or frequency setting input. connect a resistor to ground from this pin sets the switching frequency. force this pin to v dd or gnd causes the device to be shut down. 2, 11 (exposed pad) 2, 9 (exposed pad) gnd signal ground. all small-signal components and compensation components should be connected to this ground, which in turn connects to pgnd at one point. the exposed pad must be soldered to a large pcb and connected to gnd for maximum power dissipation. 3, 4 3 lx internal power mosfet switches output. connect this pin to the inductor. 5 4 pgnd power ground. connect this pin close to the negative terminal of c in and c out . 6, 7 5 pvdd power supply input. decouple this pin to pgnd with a capacitor. 8 6 vdd signal supply input. decouple this pin to gnd with a capacitor. generally, v dd is equal to pvdd. 9 7 fb feedback pin. this pin receives the feedback voltage from a resistive divider connected across the output. 10 8 comp error amplifier compensation point. the current comparator threshold increases with this control voltage. connect external compensation elements to this pin to stabilize the control loop. function block diagram driver control logic oc limit isen slope comp. osc output clamp ea 0.8v internal - soft star por gnd fb pvdd vdd pgnd lx otp vref sd nisen n-mosfet i lim 0.7v 0.4v shdn/rt comp
RT8055 4 ds8055-05 november 2012 www.richtek.com ? copyright 2012 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. absolute maximum ratings (note 1) z supply input voltage, vdd, pv dd ---------------------------------------------------------------------------- ? 0.3v to 6.5v z lx pin switch voltage -------------------------------------------------------------------------------------------- ? 0.3v to (pvdd + 0.3v) <10ns ---------------------------------------------------------------------------------------------------------------- ? 5v to 8.5v z other i/o pin v oltages ------------------------------------------------------------------------------------------- ? 0.3v to 6.5v z lx pin switch current -------------------------------------------------------------------------------------------- 4a z power dissipation, p d @ t a = 25 c wdfn-10l 3x3 ----------------------------------------------------------------------------------------------------- 1.667w sop-8 (exposed pad) ------------------------------------------------------------------------------------------- 1.333w z package thermal resistance (note 2) wdfn-10l 3x3, ja ----------------------------------------------------------------------------------------------- 60 c/w wdfn-10l 3x3, jc ----------------------------------------------------------------------------------------------- 7.8 c/w sop-8 (exposed pad), ja ------------------------------------------------------------------------------------- 75 c/w sop-8 (exposed pad), jc ------------------------------------------------------------------------------------- 15 c/w z junction temperature --------------------------------------------------------------------------------------------- 150 c z lead temperature (soldering, 10 sec.) ------------------ ----------------------------------------------------- 260 c z storage temperature range ------------------------------------------------------------------------------------ ? 65 c to 150 c z esd susceptibility (note 3) hbm (human body model) -------------------------------------------------------------------------------------- 2kv electrical characteristics (v dd = 3.3v, t a = 25 c, unless otherwise specified) recommended operating conditions (note 4) z supply input voltage ---------------------------------------------------------------------------------------------- 2.6v to 5.5v z junction temperature range ------------------------------------------------------------------------------------ ? 40 c to 125 c z ambient temperature range ------------------------------------------------------------------------------------ ? 40 c to 85 c parameter symbol test conditions min typ max unit input voltage range v dd 2.6 -- 5.5 v feedback reference voltage v ref 0.784 0.8 0.816 v feedback leakage current i fb v fb = 3.3v -- -- 0.1 a active , v fb = 0.7v, not switching -- 500 -- a dc bias current shutdown -- -- 1 a output voltage line regulation v line v in = 2.6v to 5.5v -- 0.1 -- %/v output voltage load regulation v load v in = 5v, v out = 3.3v, i out = 0a to 3a -- 0.4 -- % error amplifier transconductance gm -- 400 -- a/v current sense transresistance r s -- 0.4 -- rt leakage current shdn/rt = v in = 5.5v -- -- 1 a
RT8055 5 ds8055-05 november 2012 www.richtek.com ? copyright 2012 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. note 1. stresses beyond those listed ? absolute maximum ratings ? may cause permanent damage to the device. these are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. exposure to absolute maximum rating conditions may affect device reliability. note 2. ja is measured at t a = 25 c on a high effective thermal conductivity four-layer test board per jedec 51-7. jc is measured at the exposed pad of the package. note 3. devices are esd sensitive. handling precaution is recommended. note 4. the device is not guaranteed to function outside its operating conditions. note 5. guaranteed by design. parameter symbol test conditions min typ max unit r osc = 180k 1.44 1.8 2.16 switching frequency adjustable switching frequency range 0.3 -- 2 mhz switch on resistance, high r ds(on)_p i sw = 0.3a -- 100 160 m switch on resistance, low r ds(on)_n i sw = 0.3a -- 100 170 m peak current limit i lim 3.5 -- -- a v dd rising @full temperature 2.33 2.4 2.57 under voltage lockout threshold (note 5) v dd falling @full temperature 1.98 2.2 2.37 v shutdown threshold v shdn v shdn rising -- v in ? 0.85 v in ? 0.4 v
RT8055 6 ds8055-05 november 2012 www.richtek.com ? copyright 2012 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. typical operating characteristics output voltage vs. input voltage 3.30 3.31 3.32 3.33 3.34 3.35 3.36 3.5 3.7 3.9 4.1 4.3 4.5 4.7 4.9 5.1 5.3 5.5 input voltage (v) output voltage (v) i out = 0a, v out = 3.3v output voltage vs. output current 3.26 3.27 3.28 3.29 3.30 3.31 3.32 3.33 3.34 3.35 3.36 3.37 3.38 0.0 0.3 0.6 0.9 1.2 1.5 1.8 2.1 2.4 2.7 3.0 output current (a) output voltage (v) v in = 5v, v out = 3.3v efficiency vs. output current 0 10 20 30 40 50 60 70 80 90 100 0.0 0.3 0.6 0.9 1.2 1.5 1.8 2.1 2.4 2.7 3.0 output current (a) efficiency (%) v in = 5v, v out = 3.3v switching frequency vs. temperature 1.5 1.6 1.7 1.8 1.9 2.0 2.1 -50 -25 0 25 50 75 100 125 temperature (c) switching frequency (mhz) 1 v in = 5v, v out = 3.3v i out = 0.3a, f sw = 1.8mhz switching frequency vs. input voltage 1.5 1.6 1.7 1.8 1.9 2.0 2.1 3.5 3.7 3.9 4.1 4.3 4.5 4.7 4.9 5.1 5.3 5.5 input voltage (v) switching frequency (mhz) 1 v in = 5v, v out = 3.3v i out = 0.3a, f sw = 1.8mhz v in uvlo vs. temperature 2.00 2.05 2.10 2.15 2.20 2.25 2.30 2.35 2.40 2.45 2.50 -50 -25 0 25 50 75 100 125 temperature (c) v in uvlo (v) rising falling v out = 3.3v
RT8055 7 ds8055-05 november 2012 www.richtek.com ? copyright 2012 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. output ripple time (500ns/div) v in = 5v, v out = 3.3v i out = 0a v lx (5v/div) v out (5mv/div) output ripple time (500ns/div) v in = 5v, v out = 3.3v i out = 3a v lx (5v/div) v out (5mv/div) reference voltage vs. temperature 0.760 0.768 0.776 0.784 0.792 0.800 0.808 0.816 0.824 0.832 0.840 -50 -25 0 25 50 75 100 125 temperature (c) reference voltage (v) output current limit vs. temperature 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 -50 -25 0 25 50 75 100 125 temperature (c) output current limit (a ) v in = 5v, v out = 3.3v output current limit vs. input voltage 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 3.5 3.7 3.9 4.1 4.3 4.5 4.7 4.9 5.1 5.3 5.5 input voltage (v) output current limit (a ) v out = 3.3v output voltage vs. temperature 3.20 3.22 3.24 3.26 3.28 3.30 3.32 3.34 3.36 3.38 3.40 -50 -25 0 25 50 75 100 125 temperature (c) output voltage (v) v in = 5v, v out = 3.3v i out = 0a
RT8055 8 ds8055-05 november 2012 www.richtek.com ? copyright 2012 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. power on from v in time (1ms/div) v in = 5v, v out = 3.3v i out = 0a v lx (5v/div) v in (2v/div) v out (1v/div) load transient response time (100 s/div) i out (1a/div) v out (200mv/div) v in = 5v, v out = 3.3v i out = 0a to 2a load transient response time (100 s/div) i out (1a/div) v out (200mv/div) v in = 5v, v out = 3.3v i out = 0a to 3a uvp shutdown time (10 s/div) v lx (5v/div) v out (1v/div) v in = 5v, v out = 3.3v
RT8055 9 ds8055-05 november 2012 www.richtek.com ? copyright 2012 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. application information the basic RT8055 application circuit is shown in typical application circuit. external component selection is determined by the maximum load current and begins with the selection of the inductor value and operating frequency followed by c in and c out . output voltage setting the output voltage is set by an external resistive divider according to the following equation : figure 1. setting the output voltage ? ? ? ? ? ? + = r2 r1 1 v v ref out soft-start the RT8055 contains an internal soft-start clamp that gradually raises the clamp on the comp pin. operating frequency selection of the operating frequency is a tradeoff between efficiency and component size. high frequency operation allows the use of smaller inductor and capacitor values. operation at lower frequency improves efficiency by reducing internal gate charge and switching losses but requires larger inductance and/or capacitance to maintain low output ripple voltage. the operating frequency of the RT8055 is determined by an external resistor that is connected between the shdn/ rt pin and gnd. the value of the resistor sets the ramp current that is used to charge and discharge an internal timing capacitor within the oscillator. the rt resistor value can be determined by examining the frequency vs. r rt curve. although frequencies as high as 2mhz are possible, the minimum on-time of the RT8055 imposes a minimum limit on the operating duty cycle. the minimum on-time is typically 110ns. therefore, the minimum duty cycle is equal to 100 x 110ns x f (hz). figure 2 RT8055 fb gnd v out r1 r2 100% duty cycle operation when the input supply voltage decreases toward the output voltage, the duty cycle increases toward the maximum on-time. further reduction of the supply voltage forces the main switch to remain on for more than one cycle eventually reaching 100% duty cycle. the output voltage will then be determined by the input voltage minus the voltage drop across the internal p-mosfet and the inductor. low supply operation the RT8055 is designed to operate down to an input supply voltage of 2.6v. one important consideration at low input supply voltages is that the r ds(on) of the p-channel and n-channel power switches increases. the user should calculate the power dissipation when the RT8055 is used at 100% duty cycle with low input voltages to ensure that thermal limits are not exceeded. slope compensation and inductor peak current slope compensation provides stability in constant frequency architectures by preventing sub-harmonic oscillations at duty cycles greater than 50%. it is accomplished internally by adding a compensating ramp to the inductor current signal. normally, the maximum inductor peak current is reduced when slope compensation is added. in the RT8055, however, separated inductor current signals are used to monitor over current condition. 0.0 0.5 1.0 1.5 2.0 2.5 3.0 0 200 400 600 800 1000 r osc (k ) switching frequency (mhz) 1 r osc (k ) r rt = 180k for 1.8mhz where v ref equals to 0.8v typical. the resistive divider allows the fb pin to sense a fraction of the output voltage as shown in figure 1.
RT8055 10 ds8055-05 november 2012 www.richtek.com ? copyright 2012 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. this formula has a maximum at v in = 2v out , where i rms = i out /2. this simple worst-case condition is commonly used for design because even significant deviations do not offer much relief. choose a capacitor rated at a higher temperature than required. several capacitors may also be paralleled to meet size or height requirements in the design. the selection of c out is determined by the effective series resistance (esr) that is required to minimize voltage ripple and load step transients, as well as the amount of bulk capacitance that is necessary to ensure that the control loop is stable. loop stability can be checked by viewing the load transient response as described in a later section. the output ripple, v out , is determined by : 1 v v v v i i out in in out out(max) rms ? = ? ? ? ? ? ? + out l out 8fc 1 esr i v this keeps the maximum output current relatively constant regardless of duty cycle. short circuit protection when the output is shorted to ground, the inductor current decays very slowly during a single switching cycle. a current runaway detector is used to monitor inductor current. as current increasing beyond the control of current loop, switching cycles will be skipped to prevent current runaway from occurring. inductor selection the inductor value and operating frequency determine the ripple current according to a specific input and output voltage. the ripple current i l increases with higher v in and decreases with higher inductance. out out l in vv i = 1 fl v ??? ? ?? ??? ? ??? ? out out l(max) in(max) vv l = 1 fi v ??? ? ? ??? ? ??? ? having a lower ripple current reduces not only the esr losses in the output capacitors but also the output voltage ripple. however, it requires a large inductor to achieve this goal. for the ripple current selection, the val ue of i l = 0.4(i max ) will be a reasonable starting point. the large st ripple current occurs at the highest v in . to guarantee that the ripple current stays below the specified maximum, the inductor value should be chosen according to the following equation : the inductor's current rating (caused a 40 c temperature rising from 25 c ambient) should be greater than the maximum load current and its saturation current should be greater than the short circuit peak current limit. c in and c out selection the input capacitance, c in , is needed to filter the trapezoidal current at the source of the top mosfet. to prevent large ripple voltage, a low esr input capacitor sized for the maximum rms current should be used. rms current is given by : the output ripple is highest at maximum input voltage since i l increases with input voltage. multiple capacitors placed in parallel may be needed to meet the esr and rms current handling requirements. dry tantalum, special polymer, aluminum electrolytic and ceramic capacitors are all available in surface mount packages. special polymer capacitors offer very low esr but have lower capacitance density than other types. tantalum capacitors have the highest capacitance density but it is important to only use types that have been surge tested for use in switching power supplies. aluminum electrolytic capacitors have significantly higher esr but can be used in cost-sensitive applications provided that consideration is given to ripple current ratings and long term reliability. ceramic capacitors have excellent low esr characteristics but can have a high voltage coefficient and audible piezoelectric effects. the high q of ceramic capacitors with trace inductance can also lead to significant ringing. using ceramic input and output capacitors higher values, lower cost ceramic capacitors are now becoming available in smaller case sizes. their high ripple current, high voltage rating and low esr make them ideal for switching regulator applications. however, care must be taken when these capacitors are used at the input and output. when a ceramic capacitor is used at the input
RT8055 11 ds8055-05 november 2012 www.richtek.com ? copyright 2012 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. and the power is supplied by a wall adapter through long wires, a load step at the output can induce ringing at the input, v dd . at best, this ringing can couple to the output and be mistaken as loop instability. at worst, a sudden inrush of current through the long wires can potentially cause a voltage spike at v in large enough to damage the part. thermal considerations for continuous operation, do not exceed absolute maximum junction temperature. the maximum power dissipation depends on the thermal resistance of the ic package, pcb layout, rate of surrounding airflow, and difference between junction and ambient temperature. the maximum power dissipation can be calculated by the following formula : p d(max) = (t j(max) ? t a ) / ja where t j(max) is the maximum junction temperature, t a is the ambient temperature, and ja is the junction to ambient thermal resistance. for recommended operating condition specifications, the maximum junction temperature is 125 c. the junction to ambient thermal resistance, ja , is layout dependent. for sop-8 (exposed pad) packages, the thermal resistance, ja , is 75 c/w on a standard jedec 51-7 four-layer thermal test board. for wdfn-10l 3x3 packages, the thermal resistance, ja , is 70 c/w on a standard jedec 51-7 four-layer thermal test board. the maximum power dissipation at t a = 25 c can be calculated by the following formulas : p d(max) = (125 c ? 25 c) / (75 c/w) = 1.333w for sop-8 (exposed pad) package p d(max) = (125 c ? 25 c) / (70 c/w) = 1.429w for wdfn-10l 3x3 package the maximum power dissipation depends on the operating ambient temperature for fixed t j(max) and thermal resistance, ja . the derating curves in figure 3 allow the designer to see the effect of rising ambient temperature on the maximum power dissipation. figure 3. derating curve of maximum power dissipation layout considerations follow the pcb layout guidelines for optimal performance of RT8055. ` a ground plane is recommended. if a ground plane layer is not used, the signal and power grounds should be segregated with all small-signal components returning to the gnd pin at one point that is then connected to the pgnd pin close to the ic. the exposed pad should be connected to gnd. ` connect the terminal of the input capacitor(s), c in , as close as possible to the pvdd pin. this capacitor provides the ac current into the internal power mosfets. ` lx node is with high frequency voltage swing and should be kept within small area. keep all sensitive small-signal nodes away from the lx node to prevent stray capacitive noise pick-up. ` flood all unused areas on all layers with copper. flooding with copper will reduce the temperature rise of powercomponents. you can connect the copper areas to any dc net (pvdd, vdd, vout, pgnd, gnd, or any other dc rail in your system). ` connect the fb pin directly to the feedback resistors. the resistor divider must be connected between v out and gnd. 0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.3 1.4 1.5 0 25 50 75 100 125 ambient temperature (c) maximum power dissipation (w) wdfn-10l 3x3 four-layer pcb sop-8 (exposed pad)
RT8055 12 ds8055-05 november 2012 www.richtek.com ? copyright 2012 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. component supplier series inductance ( h) dcr (m ) current rating (ma) dimensions (mm) taiyo yuden nr 8040 2 9 7800 8x8x4 component supplier part no. capacitance ( f) case size tdk c3225x5r0j226m 22 1210 tdk c2012x5r0j106m 10 0805 panasonic ecj4yb0j226m 22 1210 panasonic ecj4yb1a106m 10 1210 taiyo yuden lmk325bj226ml 22 1210 taiyo yuden jmk316bj226ml 22 1206 taiyo yud en jmk212bj106ml 10 0805 table 2. inductors table 3. capacitors for c in and c out recommended component selection for typical application figure 4. pcb layout guide v out shdn/rt gnd pgnd lx comp fb vdd pvdd pvdd lx 9 8 7 1 2 3 4 5 10 6 gnd 11 r osc r comp c comp r2 r1 c f v out gnd v in l1 c out c in c in must be placed between v dd and gnd as closer as possible lx should be connected to inductor by wide and short trace, keep sensitive compontents away from this trace output capacitor must be near RT8055 connect the fb pin directly to feedback resistors. the resistor divider must be connected between v out and gnd.
RT8055 13 ds8055-05 november 2012 www.richtek.com ? copyright 2012 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. outline dimension dimensions in millimeters dimensions in inches symbol min max min max a 0.700 0.800 0.028 0.031 a1 0.000 0.050 0.000 0.002 a3 0.175 0.250 0.007 0.010 b 0.180 0.300 0.007 0.012 d 2.950 3.050 0.116 0.120 d2 2.300 2.650 0.091 0.104 e 2.950 3.050 0.116 0.120 e2 1.500 1.750 0.059 0.069 e 0.500 0.020 l 0.350 0.450 0.014 0.018 w-type 10l dfn 3x3 package 1 1 2 2 note : the configuration of the pin #1 identifier is optional, but must be located within the zone indicated. det ail a pin #1 id and tie bar mark options d 1 e a3 a a1 d2 e2 l b e see detail a
RT8055 14 ds8055-05 november 2012 www.richtek.com richtek technology corporation 5f, no. 20, taiyuen street, chupei city hsinchu, taiwan, r.o.c. tel: (8863)5526789 richtek products are sold by description only. richtek reserves the right to change the circuitry and/or specifications without notice at any time. customers should obtain the latest relevant information and data sheets before placing orders and should verify that such information is current and complete. richtek cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a richtek product. information furnish ed by richtek is believed to be accurate and reliable. however, no responsibility is assumed by richtek or its subsidiaries for its use; nor for any infringeme nts of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of r ichtek or its subsidiaries. a b j f h m c d i y x exposed thermal pad (bottom of package) 8-lead sop (exposed pad) plastic package dimensions in millimeters dimensions in inches symbol min max min max a 4.801 5.004 0.189 0.197 b 3.810 4.000 0.150 0.157 c 1.346 1.753 0.053 0.069 d 0.330 0.510 0.013 0.020 f 1.194 1.346 0.047 0.053 h 0.170 0.254 0.007 0.010 i 0.000 0.152 0.000 0.006 j 5.791 6.200 0.228 0.244 m 0.406 1.270 0.016 0.050 x 2.000 2.300 0.079 0.091 option 1 y 2.000 2.300 0.079 0.091 x 2.100 2.500 0.083 0.098 option 2 y 3.000 3.500 0.118 0.138

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